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module Lab8( CLK, PDout, PDin, Reset, ssO, AN, AC ); input PDout, PDin; input CLK, Reset; output [6:0]ssO; output [3:0] AN; output AC; wire [1:0] w1; reg [3:0] w4, w5; wire [4:0] w3; wire [6:0] w6, w7, w8; //reg [4:0] w12; //initial begin //w12 = 5'b01010; //end Steytir cokMuhimModul(CLK, PDout, PDin, Reset, w1); Counter CNTR(w1, AC, w3, CLK, Reset); //w3 is OutToSS in Counter module always @(w3) begin w4 = {w3[3],w3[2],w3[1],w3[0]}; w5 = {3'b000, w3[4]}; end SevenSegment S1(w6, w4); SevenSegment S2(w7, w5); DualSevenSegment DualSS(w8, AN, w6, w7, CLK); assign ssO = ~w8; endmodule module Counter(IncDec, AC, OutToSS, Clk, Reset ); input Clk, Reset; input [1:0] IncDec; output [4:0] OutToSS; output AC; reg AC; reg [4:0] OutToSS; always @(posedge Clk) begin //reset function if (Reset) begin OutToSS <= 5'b00000; end //when increment signal is 1, increment OutToSS by 1 else if (!IncDec[0] && IncDec[1]) OutToSS <= OutToSS + 1; //when decrement signal is 1, decrement OutToSS by 1 else if (IncDec[0] && !IncDec[1] && OutToSS!=0) OutToSS <= OutToSS - 1; else OutToSS <= OutToSS; end //air conditioning //open air condition when OutToSS is 01000 //close it when OutToSS is 00111 and 00000 always @ (OutToSS or Reset) begin if(OutToSS == 5'b00111) AC <= 1'b0; else if(OutToSS == 5'b01000) AC <= 1'b1; else if(OutToSS == 5'b00000) AC <= 1'b0; end endmodule module Steytir(CLK, PDout, PDin, Reset, IncDec ); input CLK, PDout, PDin, Reset; output [1:0] IncDec; reg [2:0] state, next_state; parameter A=3'b000, B=3'b001, C=3'b010, D=3'b011, E=3'b100, F=3'b101, G=3'b110, H=3'b111; reg [1:0]IncDec; //reset function always @(posedge CLK) begin if(Reset) begin state <= A; end else begin state <= next_state; end end //state machine implementation /*always @(PDout or PDin or state) begin case (state) A: if ((PDin == 1) && (PDout == 0)) next_state <= B; else if ((PDin == 0) && (PDout == 1)) next_state <= E; else if ((PDin == 1) && (PDout == 1)) next_state <= A; B: if ((PDin == 0) && (PDout == 1)) next_state <= B; else if ((PDin == 0) && (PDout == 0)) next_state <= C; C: if ((PDin == 0) && (PDout == 0)) next_state <= C; else if ((PDin == 0) && (PDout == 1)) next_state <= D; D: if ((PDin == 0) && (PDout == 1)) next_state <= D; else if ((PDin == 1) && (PDout == 1)) next_state <= A; E: if ((PDin == 0) && (PDout == 1)) next_state <= E; else if ((PDin == 0) && (PDout == 0)) next_state <= F; F: if ((PDin == 0) && (PDout == 0)) next_state <= F; else if ((PDin == 1) && (PDout == 0)) next_state <= G; G: if ((PDin == 1) && (PDout == 0)) next_state <= G; else if ((PDin == 1) && (PDout == 1)) next_state <= A; endcase end //output function always @ (PDout or PDin or state) begin case(state) A: begin Inc <= 0; Dec <=0; end B: begin Inc <= 0; Dec <=0; end C: begin Inc <= 0; Dec <=0; end //d'den gelince increment olcak D: if((PDin == 1) && (PDout ==1)) begin Inc <= 1; //bura 1di hehe Dec <=0; end else begin Inc <= 0; Dec <= 0; end E: begin Inc <= 0; Dec <=0; end F: begin Inc <= 0; Dec <=0; end //g'den gelince decrement olcak G: if((PDin == 1) && (PDout ==1)) begin Inc <= 0; Dec <= 1; end else begin Inc <= 0; Dec <= 0; end endcase */ //state function always @(PDin or PDout or state) begin case(state) A : begin if(PDin && PDout) next_state <= B; else next_state <= A; end B : begin if(PDout && PDin) next_state <= B; else if(PDout && ~PDin) next_state <= D; else if(~PDout && PDin) next_state <= C; else next_state <= A; end C : begin if(PDout && PDin) next_state <= B; else if(PDout && ~PDin) next_state <= A; else if(~PDout && PDin) next_state <= C; else next_state <= E; end D : begin if(PDout && PDin) next_state <= B; else if(PDout && ~PDin) next_state <= D; else if(~PDout && PDin) next_state <= D; else next_state <= F; end E : begin if(PDout && PDin) next_state<=B; else if(PDout && ~PDin) next_state <= G; else if(~PDout && PDin) next_state <= C; else next_state <= E; end F : begin if(PDout && PDin) next_state <= B; else if(PDout && ~PDin) next_state <= D; else if(~PDout && PDin) next_state <= H; else next_state <= F; end G : begin if(PDout && PDin) next_state <= B; else if(PDout && ~PDin) next_state <= G; else if(~PDout && PDin) next_state <= C; else next_state <= E; end H : begin if(PDout && PDin) next_state<=B; else if(PDout && ~PDin) next_state<=D; else if(~PDout && PDin) next_state<=H; else next_state <= F; end endcase end //output function always@(PDout or PDin or IncDec or next_state or state) begin if((state == G) && PDout && PDin) IncDec<= 2'b10; else if((state == H) && PDout && PDin) IncDec<= 2'b01; else IncDec <= 2'b00; end endmodule
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